Muqi Xu
Hi, I’m Barry! I’m a computer engineer passionate about RTL design, design verification, and computer architecture, particularly for AI computing systems.
I enjoy exploring every layer of the computing stack: from ML applications and parallel programming, through operating systems and microarchitecture, down to verification, circuits, and boards. I believe understanding how these layers interact helps me better evaluate design decisions and navigate system-level trade-offs.
Slow is smooth. Smooth is fast.
As AI accelerates the pace of innovation, I believe it’s more important than ever to build a solid foundation rather than simply chase the latest technology.
I value curiosity, deliberate learning, and understanding not just how something works, but why it works and what could make it better.
From models to transistors
Project details are being updated one by one, with more write-ups and diagrams coming soon.
HandGest: edge-TPU hand gesture recognition
Two-stage MobileNetV2 pipeline (hand detector + 5-class gesture classifier), trained and quantized to full INT8 for the Coral Edge TPU on a Raspberry Pi 5. Studied multi-model cache behavior and sped up inference with co-compilation and dual-TPU execution.
GPT-2 transformer acceleration in CUDA
Full GPT-2 forward pass including multi-head attention. Optimized matmul with shared-memory tiling and register reuse, integrated CUTLASS with TF32 tensor cores, and profiled bottlenecks in Nsight Compute.
RISC-V operating system kernel
Sv39 virtual memory, buddy physical allocator, Unix-style fork, preemptive scheduling, block-level filesystem caching, and lock-based synchronization.
16-core SIMD GPU on FPGA
Validated a custom 16-core GPU by building a Super Mario demo in C that exercises its instructions and memory system. Debugged HW/SW integration issues.
Two-way superscalar out-of-order RISC-V CPU
RV32IM with explicit register renaming (ROB, RAT/RRAT, free list, PRF), reservation stations, split load/store queues, GShare + RAS, a pipelined cache path, and compressed instructions. Verified with directed and random instruction tests in VCS/Verdi.
UVM environment for a 4×4 INT8 matrix-multiply tile
Reusable agents, drivers, monitors, sequencers, and scoreboards for a valid/ready streaming interface. Constrained-random stimulus across scaling, ReLU, saturation, overflow, and backpressure. Found multiple RTL bugs through waveform debug.
Custom RISC-V datapath and standard-cell flow
Custom CMOS standard cells and a bit-sliced RV32I datapath, from schematic and transistor sizing to layout. Passed DRC/LVS, generated Liberty/LEF views, and explored place-and-route in Innovus.
OpenPeriph: RF hardware interface for AI agents
Two-layer PCB linking PC-side AI agents to physical peripherals via an STM32F411, CC1101 RF transceiver, USB-CDC, and e-paper display. Firmware for packet parsing, CRC, and RF retry/timeout.
Clock module PCB design and bring-up
Schematic and layout in Altium, PCBA bring-up with oscilloscope and multimeter, and standardized symbol/footprint libraries for the team.
- Hardware & verification
- RTL design, out-of-order microarchitecture, UVM, constrained-random, functional coverage, valid/ready protocols
- Languages
- SystemVerilog, C/C++, Python, CUDA, RISC-V assembly, Java
- EDA & tools
- Synopsys VCS / Verdi, Cadence Virtuoso / Innovus, Xilinx Vivado / Vitis, Altium, Nsight Compute, Git, GDB
- Platforms
- FPGA, Coral Edge TPU, Raspberry Pi 5, STM32, ESP32